The present invention relates generally to semiconductor devices and more particularly to a semiconductor memory device having a substrate potential detection circuit for allowing a stable substrate potential level to be generated and maintained.
Semiconductor devices have been equipped with substrate potential generators (such as back bias generators) that generate a voltage potential to be applied to the substrate or a well. By applying a potential bias to the substrate, various improvements to circuit operation have been made.
In a semiconductor memory device, such as a dynamic random access memory (DRAM), the substrate has typically had a potential bias applied. This has been done for various reasons. One reason is to improve latch-up characteristics by decreasing the possibility of forward biasing p-n junctions that are formed between sources or drains of transistors and the substrate. Also, a biased substrate has the affect of decreasing junction capacitance. Another affect is an increase in threshold voltages of transistors formed in the substrate. In a DRAM memory array, a biased substrate can improve cell-to-cell isolation by keeping undesired transistors (thick field devices) from being formed between memory cells. It can also decrease sub-threshold leakage in the memory cell transistor by increasing the cell transistor""s threshold voltage.
For example, in a conventional DRAM memory cell the threshold voltage VT of a memory cell transistor is about 1.2 V and the substrate potential (back bias potential) is set to about xe2x88x922 V.
In order to decrease the chip size of a semiconductor memory, such as a DRAM, device sizes are continuously made smaller. In the memory cell array, the memory cell transistor can have a gate length that is reduced. This can cause the memory cell transistor""s threshold voltage VT to be reduced, which can contribute to charge leaking from a memory cell capacitor through the transistor by way of sub-threshold leakage.
Also, due to the memory cell transistor gate length becoming smaller, the depletion region formed by the p-n junctions of the source/drain regions to the substrate can be excessively large with respect to the gate length. In order to narrow these depletion regions, a higher concentration of dopant is implanted in the substrate. However, the narrower depletion region results in a higher electric field intensity. This higher electric field intensity can result in an increased charge leakage from the memory cell storage capacitor to the substrate by way of the p-n junction.
These charge leakage paths from the memory cell storage capacitor shorten the amount of time that charge can be held on the capacitor. This affects data integrity, in particular, the pause/refresh characteristics of the DRAM and decreases the reliability of the DRAM.
It is desired to keep the VT of the memory cell transistor at an adequate value while providing a minimum gate length. However, the substrate potential needs to be set at about xe2x88x920.5 V to limit the intensity of the electric field at the p-n junction formed from the memory cell capacitor contact (source/drain region of memory cell transistor) and the substrate.
Current may flow to the substrate during various operating conditions of a DRAM. One example of an operating condition in which a relatively large amount of current can flow to the substrate is a data sensing operation. In a DRAM, due to the destructive nature of a read and the large number of memory cells selected during a read of a single bit, a large number of sense amplifiers are activated simultaneously. Each sense amplifier is biased in such a condition that a relatively large amount of current is injected into the substrate during the sensing operation. This can drastically affect the substrate potential.
In order to keep the substrate potential at about xe2x88x920.5 V, an accurate substrate potential detector circuit is needed. Based on an output of the substrate potential detector circuit a substrate potential generator (substrate pump) can either be enabled or disabled based on whether the substrate potential is above or below xe2x88x920.5 V.
One example of a conventional substrate voltage detector circuit has been disclosed in Japanese Patent Publication No. Hei 2-3153. Referring now to FIG. 1, a conventional substrate voltage detector circuit as disclosed in Japanese Patent Publication No. Hei 2-3153 is set forth in a circuit schematic diagram and given the general reference character 100.
Conventional substrate voltage detector circuit 100 includes P-type metal-oxide-semiconductor field effect transistors (MOSFET) (101, 103, and 104) and N-type MOSFETs (102 and 105). P-type MOSFET 103 has a source connected to supply voltage VCC, a drain connected to detection node N2 and a gate connected to ground voltage VSS. P-type MOSFET 101 has a source connected to a source of N-type MOSFET 102 and a drain and gate connected to the substrate potential VBB. N-type MOSFET 102 has a drain connected to detection node N2 and a gate connected to supply voltage VCC.
P-type MOSFET 104 has a source connected to supply voltage VCC, a drain connected to substrate level detect signal node N3, and a gate connected to detection node N2. N-type MOSFET 105 has a source connected to ground voltage VSS, a drain connected to substrate level detect signal node N3, and a gate connected to detection node N2. P-type MOSFET 104 and N-type MOSFET 105 form an inverter 106.
The operation of conventional substrate voltage detector circuit 100 will now be described.
P-type MOSFET 103 and N-type MOSFET 102 have gate voltages that keep both MOSFETs (102 and 103) in a conducting state. P-type MOSFET 103 and N-type MOSFET 102 form a voltage divider circuit with P-type MOSFET 103 having a resistance of R2 and N-type MOSFET 102 having a resistance of R1. If P-type MOSFET 101 is relatively large compared to P-type MOSFET 103 and N-type MOSFET 102, the detection node potential VA at detection node N2 is given by the following equation: VA=(R1/(R1+R2))xc3x97VCC+(R1/(R1+R2))xc3x97(VBB+VT), where VT is the threshold voltage of P-type MOSFET 101.
When the detection node potential VA falls below the trip point of inverter 106, substrate level detect signal node N3 becomes logic high. When the detection node potential VA rises above the trip point of inverter 106, substrate level detect signal node N3 becomes logic low.
Because the detection node potential VA is dependent on the substrate potential VBB, when substrate potential VBB falls below a predetermined potential, level detect signal node N3 becomes logic high. When substrate potential VBB rises above a predetermined potential, level detect signal node N3 becomes logic low. When at a logic low, level detect signal N3 activates an oscillator (not shown). When at a logic high, level detect signal N3 disables the oscillator. The oscillator is connected to a substrate pump (also not shown) and in this manner, the substrate potential VBB is regulated.
Another example of a conventional substrate voltage detector circuit has been disclosed in Japanese Laid-Open Patent Publication No. Hei 6-303765. Referring now to FIG. 2, a conventional substrate voltage detector circuit as disclosed in Japanese Laid-Open Patent Publication No. Hei 6-303765 is set forth in a circuit schematic diagram and given the general reference character 200.
Conventional substrate voltage detector circuit 200 includes voltage dividers 211 and 212, differential amplifier 218, inverters (219 and 220) and latching circuit 221.
Voltage divider 211 includes resistors (213 and 214). Resistor 213 is connected between a supply voltage VCC and a reference node N201. Resistor 214 is connected between a reference node N201 and a ground voltage VSS.
Voltage divider 212 includes resistors (215, 216 and 217). Resistor 215 is connected between a supply voltage VCC and a substrate reference node N202. Resistor 216 is connected between a substrate reference node N202 and resistor 216. Resistor 217 is connected between resistor 216 and a substrate potential VBB.
Differential amplifier 218 has a positive input connected to reference node N201, a negative input connected to substrate reference node N202, and an output VOUT connected to an input of inverter 219. Inverter 219 has an output connected to an input of inverter 220. Inverter 220 has an output connected to an input of latching circuit 221. Latching circuit 221 provides a substrate level detect signal xcfx86UP. Latching circuit 221 has two inverters (222 and 223), each having a respective output connected to the respective input of the other.
The operation of conventional substrate voltage detector circuit 200 will now be described.
A reference potential VCCREF is generated at reference node N201 as determined by the values of the resistance of resistors (213 and 214). A substrate reference VBBREF is generated at reference node N202 as determined by the values of the resistance of resistors (215, 216, and 217). If substrate reference potential VBBREF is higher than reference potential VCCREF, then the output VOUT of differential amplifier 218 goes low and substrate level detect signal xcfx86UP goes high. If substrate reference potential VBBREF is lower than reference potential VCCREF, then the output VOUT of differential amplifier 218 goes high and substrate level detect signal xcfx86UP goes low.
Because the substrate reference potential VBBREF is dependent on the substrate potential VBB, when substrate potential VBB falls below a predetermined potential, substrate level detect signal xcfx86UP becomes logic low. When substrate potential VBB rises above a predetermined potential, substrate level detect signal xcfx86UP becomes logic high. When at a logic high, substrate level detect signal xcfx86UP activates an oscillator (not shown) or clock generation circuit (not shown). When at a logic low, substrate level detect signal xcfx86UP disables the oscillator or clock generation circuit. The oscillator or clock generation circuit is connected to a substrate pump (also not shown) and in this manner, the substrate potential VBB is regulated.
There are drawbacks to the conventional substrate voltage detector circuits (100 and 200) illustrated in FIGS. 1 and 2.
In conventional substrate voltage detector circuit 100 illustrated in FIG. 1, detection node potential VA is dependent upon process variations that may occur in the fabrication of MOSFETs (101, 102, and 103). Thus, the substrate potential VBB becomes dependent upon these process variations. Therefore, the substrate potential VBB can be different from chip to chip.
Also, in conventional substrate voltage detector circuit 100, the response time for the correct determination of substrate potential VBB can be slow due to both MOSFETs (104 and 105) conducting as detection node potential VA approaches the trip-point of inverter 106. If the conventional substrate voltage detector circuit 100 doesn""t respond quickly to a collapse of the substrate potential VBB, latch-up can occur during conditions, such as sensing, when the substrate current can be large.
In conventional substrate voltage detector circuit 200 illustrated in FIG. 2, resistors (213 to 217) are used to generate the substrate reference potential VBBREF and reference potential VCCREF. However, these resistors can occupy a large amount of device area, which can increase the size of the semiconductor device. This has adverse affects on the cost of manufacturing a large quantity of devices because fewer devices can be manufactured on a single wafer. Also, the voltage dividers (211 and 212) constantly conduct current. This has adverse affects to standby current in the semiconductor device. This is particularly disadvantageous in a DRAM that is to be used in a product that operates off a battery, such as a laptop computer or personal digital assistant, as just two examples.
In view of the above discussion, it would be desirable to provide a semiconductor device having a substrate potential detector circuit capable of accurately detecting a substrate potential. It would also be desirable to provide a substrate potential generator circuit including a substrate potential detector circuit, that can control the substrate potential. It would also be desirable for a substrate potential detector circuit capable of accurately detecting a substrate potential with less dependency on process variations. It would also be desirable for a substrate potential detector circuit to be capable of accurately detecting a substrate potential while occupying less device area. It would also be desirable for a substrate potential detector circuit to be capable of accurately detecting a substrate potential while consuming a lower amount of standby current.
According to the present embodiments, a semiconductor device having a substrate potential generating circuit is provided. The substrate potential generating circuit may include a pump circuit, an oscillator circuit, and a substrate potential detector circuit. Substrate potential detector circuit may include a voltage translator and differential amplifier. Voltage translator may provide a detection potential determined by the difference between an internally generated reference potential and a substrate potential. The differential amplifier may receive the detection potential and a reference potential as differential inputs and may produce a substrate potential detect signal.
According to one aspect of the embodiments, the voltage translator can include a plurality of resistive elements couple in series to form a voltage divider for providing the detection potential.
According to another aspect of the embodiments, the plurality of resistive elements may be passive resistive elements.
According to another aspect of the embodiments, the plurality of resistive elements may be IGFETs of the same conductivity type.
According to another aspect of the embodiments, the plurality of resistive elements may be IGFETs of opposite conductivity type.
According to another aspect of the embodiments, the internally generated reference potential coupled to the voltage translator in the substrate potential detector can be a supply potential for a peripheral circuit.
According to another aspect of the embodiments, internally generated reference potential coupled to the voltage translator in the substrate potential detector can be a supply potential for a sense amplifier circuit.
According to another aspect of the embodiments, the reference potential input to a reference potential terminal of the differential amplifier in the substrate potential detector can be a ground potential.
According to another aspect of the embodiments, the reference potential input to a reference potential terminal of the differential amplifier in the substrate potential detector can be an internally generated potential. The internally generated potential can be a supply potential for other circuits on the semiconductor device.
According to another aspect of the embodiments, differential amplifier in the substrate potential detector can include a current mirror load circuit.
According to another aspect of the embodiments, the substrate potential detection circuit can include a buffer circuit coupled to the differential amplifier and generating the substrate potential detect circuit.
According to another aspect of the embodiments, a reference generator can generate the internally generated reference potential coupled to the voltage translator circuit in the substrate potential detection circuit. The reference generator can include a reference circuit and a buffer circuit.
According to another aspect of the embodiments, the reference circuit can provide a reference potential dependent upon a threshold voltage of a reference device.
According to another aspect of the embodiments, the reference circuit can include a compensation device providing compensation for process and temperature variations in at least one parameter of the reference device.
According to another aspect of the embodiments, the buffer circuit in the reference generator can receive a reference potential from the reference circuit and provide the internally generated reference potential. The internally generated reference potential can have a different value than the reference potential from the reference circuit.
According to another aspect of the embodiments, the buffer circuit can include a differential amplifier and a voltage translator circuit. The differential amplifier can receive the reference potential from the reference circuit as one input and a feedback signal from the voltage translator as another input. The differential amplifier can provide a control signal for an output device of the voltage translator. The voltage translator can include a voltage divider circuit.
According to another aspect of the embodiments, substrate potential detector circuit can provide a control signal to an oscillator. The oscillator may provide an oscillator signal to a substrate pump circuit. The substrate potential may be accurately controlled.